Todays, direct conversion receivers have been heavily taken into account because of less complexity and lower costs and other benefits. But these receivers also have some disadvantages, including the imbalance between the phase-matching components and the orthogonal (IQ Imbalance) and the frequency offset of the carrier signal CFO. Which lowers the quality of the received signal or does not receive it correctly. There is two type of IQ Imbalance. Frequency-independent IQ Imbalance and Frequency Dependent IQ Imbalance Frequency-independent IQ Imbalance is due to the local oscillator (LO). And it is happen when the amplitude generated by the oscillator is not equal in the branches of I and Q, and the phase difference that the oscillator has created between the branches is not exactly 90 degrees. Frequency dependent IQ¬¬ Imbalance caused by several factors, including the unequal electronic chips in branches I and Q and unmatched low pass filters used in each branch. Algorithms are provided for each type of IQ Imbalance. But most of these algorithms suffer from high complexity and high computing power. We have first proposed a new and better precision method to estimate carrier frequency offsets. Then, with the help of calculated carrier frequency offset, an adaptive FIR filter was designed and implemented based on the LMS algorithm for frequency dependent IQ Imbalance compensation. In our proposed plan, we have tried to reduce the complexity of the computational expressions, hence the lower power consumption and the more accurate estimation. The results of the simulation of the proposed algorithm are compared with the ideal values, and the result indicates the correct operation of the proposed algorithm.

 Design of Fractional order Filters is a new field in filters design. This topic provides the control of various conditions to reach suitable filter, with an exact study of the filters behavior. It also provides more flexibility in shaping the filter response for designers. The Elliptic filter among other available filters has the fastest drop in cutoff frequency. In this thesis, the design of fractional Elliptic filter is studied exclusively; So that, the filter design is done for the fractional Laplacian operator , by the integer order approximation. In this thesis, it is shown that the fractional Elliptic filter is more similar to conditions of the proposed problem than its integer order. In addition to the second-order filter which is a common fractional order filter, higher order filters were also examined as well. In order to verify the designed filters, equivalent circuit of the transfer functions were simulated in CADENCE software, and their results were compared with obtained numerical values by MATLAB software.

 Nowadays frequency shift keying(fsk) is the most common modulation method.one of the fsk demodulator is gaussian frequency shift keying(gfsk) wich is very useful in integrated circuits. one of the demodulator common problems is use of two amplitude domain analog to digital converter for converting the amplitude of I and Q signals to digital codes. whatever the extent that the required accuracy for digital processing be More increases the complexity. Phase domain analog to digital converters are very suitable for this structure. these converters, do detecting phaseof received signal and converting it into digital code in one step and has a major role in sim;icity of circuit structure.these converters set the phase of received signal from rotated I and Q zero-crossing detectors. the PH-ADC problems are lots of resistance and block used in it. in this thesis capacitor structure is used instead of resistor network wich increase accuracy in frequency characteristic and wide dynamic range.in addition,attemps too reduce the number of comparators.this number reduce from 8 to 1 and in addition to reducing chip area.all the proposed structure simulation and compare with 0.18 um cmos transistor level thechnology.

In this thesis, analysis of low first and second order low pass filter Sigma-Delta analog to digital converter with non ideal integrator is presented. This integrator is designed with bulk-driven amplifier and 0.5V rail-to-rail voltage and 0.306uW power specifications, 52db open loop gain, phase margin of 〖38〗^o , and 1.4 MHz bandwith. in this theses, the effective input transconductance is enhaned by 14 times. In low first and second order low pass filter Sigma-Delta the input frequency is 20kHz and 10 MHz sample frequency, the over sampling ratio (OSR) is 250. The power spectifications for the first Sigma-Delta is 751.92 uW, SNR=46.62 and ENOB=7.45 and power spectifications for the second order is 1.47 mW, SNR=68.18 and ENOB=11.03, Main aspect of this design is its low power usage. Finally, first and second order non ideal analog to digital converter is implemented by HSPICE program.

 

The time-to-digital converters are widely used in industrial applications. Most of these applications can use this type of converters in laser range tracker, on chip time signals measurement, frequency synthesis circuits and reloading of capacitor sensors. Among the most important parameters describing a time-to-digital converter can refer to: time resolution, linearity range, dynamic range, time of conversion, number of bits, circuit complexity, power consuming, chip area, stability of converter again process-power supply-temperature. In this thesis, a novel time to digital converter with using of successive approximation technique is suggested that improves converter performance. Proposed converter comprises 10 one bit stages that each stage produces one bit of final digital code. This structure consists of one SR flip flop and four 2:1 multiplexer. contrary to preceding works this converter uses only one delay line for start and stop signals. Employing these types of multiplexers, switching operation will happen between delayed and without delay line. Hence, this structure has a simple circuit than the other works that improves power consumption and conversion speed. This converter was simulated in 90nm technology. The results of simulation prove the accuracy of the converter.

 The explosive proliferation of battery powered equipment in the past decade has accelerated the development and usage of power management blocks. Meanwhile a voltage regulator is one of the main building blocks of integrated circuits. Low-dropout regulator (LDO) has been used widely to provide a regulated and clean voltage source for noise-sensetive analoge subsystem, such as wireless transceivers and analoge-to-digital converter. One of the main parameters of LDOs is power supply rejection (PSR) which is ability to eliminate the supply noise. This thesis presented a low dropout voltage regulator (LDO) which has high PSR performance. Buffer stage with gm boosting techniques and PSR enhancer block and miller capacitor employed to achieve high PSR and good stability. To evaluate the performance of proposed circuits the simulations were performed by Hspice using a 180nm technology. Measured results show that the capacitor-free LDO has a stable output voltage 1.6V, when supply voltage changes from 1.8 to 3.3V, and the LDO is capable of driving maximum 100mA load current. The LDO has high power supply rejection about -77 dB at low frequency, -76 dB at 1MHz frequency and -56 dB at 10MHz frequency.

In this thesis, a low voltage charge pump has been proposed to startup a boost converter for energy harvesting applications. The startup circuit consists of two stages. These stages compose a low voltage oscillator and two high efficiency charge pump circuits, which are alternative aproaches of the Dickson charge pump. In the presented circuit, DTMOS transistors have been used to reduce the voltage threshold and to eliminate the body effect. In these types of transistors, as the threshold voltage decreases, the gate voltage increases. It results in a much higher current drive than regular MOSFET at low Vdd. The DTMOS transistors are employed for threshold voltage reduction and the efficiency increasing. Also, a method has been proposed for the clock amplitude increasing in the second stage. This increasing in the clock amplitude signal, causes a much more charge transformation in each cycle and it increases the output voltage of the circuit. In the proposed circuit, no external voltage has been used. Finally, the output voltage of the startup circuit has been used to startup a boost converter. The proposed circuit has been designed and simulated in Hspice, using 90 nm CMOS technology. According to the simulation results, the startup circuit operates with the minimum supply voltage of 100 mv and produces an output voltage of 4.6v in almost 7.2 miliseconds. With the use of this startup circuit a boost converter has been designed, which converts a 100 mv input voltage to a 3.25v output voltage within 0.2 miliseconds. Input voltage of 100mv generalizes by a Thermoelectric generator.

 The use of digital circuits with more than two logical values that are known as multiple valued logic circuits, with the potential advantage of having reduced interconnections and reduce operating units are a viable alternative to the binary logic circuits. Many logic and arithmetic functions by multi-valued logic have been implemented, better than the binary mode in areas such as the number of actuators, gate, transistors and signal transmission lines are shown. However, despite the potential benefits of these circuits, using a multivalued systems are not just learners. One reason for this is the complexity of designing a system for signal processing is multivalued. In order to solve this problem has solutions for the design and implementation of multivalued functions are provided. In the past more attention to inclusive design multivalued functions and orbital parameters in the design, particular attention has been taken. In this thesis are two ways to design and implement a multivalued functions provided in addition to being inclusive multivalued functions designed to improve the orbital parameters such as power and speed of information processing has been successful. The Maltese multivalued circuits multiplexer, adder and multiplier, because of the importance of this function, design and simulation are in two different ways. All the simulations carried out at the end of a software HSPICE and 180nm technology have been carried out.

Power amplifier is one of the main components of a telecommunications transmitters. Power amplifier is the most widely usable component of the transmitter, so the high efficiency design is important for a telecommunication transmitters. Power amplifiers are inherently nonlinear and there is inverse relationship between linear and efficiency of these amplifiers. To achieve high efficiency power amplifier can work in non-linear conditions even close to saturation, this caused many of the problems of nonlinear conditions, therefore seriously affect the quality of communications systems. A suitable procedure to solve the problems is that high efficiency amplifier design then apply a linear instrument. The purpose of this study is to analyze the types of linear instruments and provide a new structure. Since today's circuit design for better performance and higher efficiency is digital, predistortion method is considered due to implementation in the digital domain. In this study, a new digital predistortion is proposed. By using this model in indirect teaching method for power amplifier model there is no need for extracting the reverse amplifier which can be very difficult and complicated. The proposed model using nonlinear adaptive filters in the frequency domain has been implement. Implementation adaptive filters in the frequency domain which the update coefficient operations is performed in the form of block diagrams, cause reduction in the computational complexity of sum-multiply operations for the extraction of the block predistortion coefficients. The proposed predistortion will solve the problem of high volume math operations followed by power consumption and chip area. In order to evaluate the performance of the proposed predistortion, these blocks using the matlab software have been simulated. Simulation results demonstrate the accuracy of the model.

Memristor have been introduced as the fourth basic circuit element after resistor,capacitor and inductor.This device of two terminal andresistance on the nano scale range,and depends on the amplitude polarity and time duration on the applied roltage.current-voltage hysteresis curve of the memristor makes this element to act as non-volatile resistive memory and recal information until a different polarity voltage is applied,even a year later.Memristor can replace many transistors in some circuit includes a memristor and transistor could be benefits like better performance,the number of components in the chip area and power consumption is less and less to be at the same time.Dispite immense interest to scientists memristor.commercially available memristors are not expected to appear in the near future due to the cost and technical difficulties in fabricating nano-scale devices.There for,some circuit replacements which be have like memristors are needed to be build real-word application circuits which exploit memrisrtor’s potentials.
In this thesis a circuit mode ling for memristor is desined which it’s behavior is really closed to previous works.The memristor design with using a current mode multiplier and integrator.this according to it’s properties and behavior in different situations it is possible to determine the usable application.both of the structures are simulated through commercial software Hspice as well as 180 nm CMOS technology and it’s parameters is comprised with each other.The results of simulation verify the operation and efficiency of multiplication circuit parameters.

Recently, time-to-digital converters(TDCs) have mostly been used in wide variety of many industrial applications such as all digital phase locked loops, frequency synthesis circuits, and capacitive sensor readouts. These converters are used to measure of the time interval between two input signals(Start and Stop). This thesis investigates the direct and indirect methods of conversion and analyzes them. Therefore, in this study a new structure for the time-to-digital conversion is proposed which employs interpolation and time amplification techniques to improving the performance of the converter. The proposed converter is a 9-bit four stages pipeline TDC which contains of three stages 2.5b TDC and one stage 3b TDC. Compared with the similar structures, the advantages of the proposed converter are as follows: The proposed converter has a simple circuit structure and uses an analog interpolator which increases the resolution by charging and discharging of a capacitor. Also, the converter does not use delay cells in its structure. Therefore, it has a low sensitivity to PVT variations. The errors of mismatch between the elements are reduced in the converter compared with the TDCs have been previously proposed. This TDC employs the pipeline structure to digitizing the input time interval and increasing the time resolution. The proposed pipeline TDC is simulated by HSPICE in TSMC 45 nm CMOS technology. The simulated results confirm the benefits of the converter performance. TDC covers 1.60ns input range by 3.125ps resolution.

Today, measurements have influence in people's lives. Industry, commerce, medicine and science, is based on these measurements. Sensors are transducers that produce an electrical signal. Designing interface circuits to convert measurand quantity to electrical signal, is very important. Among different types of interface circuits, capacitive interfaces due to the specific characteristics of capacitance, are highly regarded. The main design challenge is to improve accuracy, expand the measurement range, reduce the complexity of circuit sensor systems, and also reducing costs. In this thesis, an interface circuit for capacitive sensors with high dynamic range is proposed. The advantages of this interface circuit are simplicity, low power consumption and the frequency output signal. To reduce the power consumption and measurement time of the capacitor, a capacitance to frequency converter is proposed that, it’s output frequency can be easily converted to digital code using a microcontroller. To increase the accuracy of the proposed system, reduce systemematic errors, and removing low frequency noise due to capacitive charge injection, automatic calibration method is used. Implementation of circuits is done with Hspice in 180 nm CMOS technology of TSMC company. According to the simulation results, the two dynamic range: from 10 fF to 1 pF and 1 pF to 100 pF are obtainable with an accuracy of %0.86.

Multiplication is one of the cornerstone operators in Mathematics which is utilized in most of the applications either generally such as microprocessors, or specifically such as digital signal processors. Microprocessors use multiplication in their mathematics calculations and digital signal processors exploit it to implement DSP algorithms namely, Fast Fourier Transform, filtering, and convolution to name but a handful. The goal of this thesis is to design a digital multiplication with sign in order to improve the parameters of the circuit in comparison to previous ones. The most momentous parameters of a digital multiplication are: loss power, delay in critical paths, occupied area, and hardware resources using to implement multiplication. In this research a new 4:2 compressor is introduced to design an integer 16 bits multiplication. This compressor is exploited in partial multiplication reduction level. The proposed 4:2 compressor is not only much more efficient than the other structures, but also utilizing it leads to minimize the key circuit parameters of multiplication. In order to evaluate the efficiency of the suggested proposal, an integer 16 bits multiplication is designed and is used in partial multiplication reduction level one time and the other time the 4:2 compressor is exploited. Both of the structures are simulated through commercial software Hspice as well as 45 nm CMOS technology and its parameter is comprised with each other. The results of simulation verify the operation and efficiency of multiplication circuit parameters.

voltage references are essential building blocks in analog and digital circuits. Their goal is to establish a stable voltage with little dependence on temperature, supply and process variations, to be used by subcircuits in electronic systems. Bandgap voltage references (BGRs) are a type of refrences that produce precision refrence voltage proportional to semiconductor bandgap energy that has a weak temperature dependence. Circuits Such as High Resolution A/D Converters Need Very stable reference. Also Todey as process technologies scale down and the demand for battery-operated portable equipment increases, the supply voltage and power consumption has to be scaled down. The proposed reference is made up of MOSFETs working in weak inversion region without resistors and bipolar transistors. Therefore the advantages of ultra-low power consumption and ultrasmall area can be obtained. Circuit operate with Low supply voltage because of lower threshold voltage in mosfets than bipolar transistors. Pervious High Order BGR Structures Based on Pre defined Value of mobility Temperature Exponent or Threshold voltage compensation Lead to Increase The Complexity of Circuit.
In Proposed BGR High order compensation in order to curvature correction of reference voltage due to temperature variation is fulfilled by cancel out the logarithmic nonlinear dependence on temperature term from VGS(T). Circuit designed in 0.18µm technology. Simulation results indicate that the proposed BGR achieves temperature coefficient(TC) of 1.4 ppm/ C^o in the Temperature Range of 0-100 C^o. Reference voltage is 487.5 mv for a supply voltage of 1.5 V and current consumption of about 24.27 μA. Circuit also consume 36.4 µwatts.

 Nowadays, the performance of telecommunication systems depends on the analog-to-digital converters. In order to have more flexibility in the next generation of communication technologies, converters with higher efficiency is required. Therefore, time-interleaving for telecommunication technologies is a perfect solution in order to enhance their efficiency. However a TI-ADC increase is throughput By means of M parallel converters, but its efficiency is reduced due to the mismatch between its different channels. Mismatch between channels, leads to the distortion of the output spectrum by generation of different output tones. This thesis, deals with the digital background calibration of gain and time mismatch. In this thesis, the mismatch error of time and gain are modeled by the first teylor series approximation and its coefficients are identified by FxLMS algorithm. Then, in order to make corrections in the error mismatch, error estimation is reduced from the output. In the next step, the weaknesses of FxLMS algorithm in a two channel TI-ADC is discussed and demonstrated with simulation results. An alternative plan is then proposed to overcome the weaknesses of FxLMS algorithm. This plan acts based on the correlation between input tone and image of the mismatch, in the whole bandwidth of two channeled TI-ADC. In order to illustrate the robustness of the proposed algorithm, conditions in which FxLMS algorithm have difficulty are taken into consideration. Four input tones with frequencies of 0.0015Fs , 0.188Fs , 0.341Fs and 0.465Fs are used as inputs for a two channel TI-ADC with the mismatch gain and time error of 0.02 and -0.01 respectively. It is worth to mention that the calibration by FxLMS algorithm fails to perform, face with frequencies of 0.0015Fs and 0.465Fs. After fault correction by the proposed algorithm, there was a 60dB improvement in output SFDR. Applying the proposed algorithm, the 80% of the performance of adding the second channel to FxLMS algorithm is saved.

With the Advancement of CMOS technology power supply voltage is reduced and switching speed is increased. Reducing the supply voltage makes it difficult to achieve high precision for voltage domain data converters. On the contrary, Increasing switching speed results better performance in time-based data converters. In data converters based on time-domain, the signal is quantized in time domain. In addition, better resolution has got. The time-domain data converters are more attractive in different applications. The data converter with two-step structure is important, because of the higher performance and improvement of some important parameters such as time resolution and accurate and etc. in this thesis, an algorithm is proposed for second stage of two-step data converter and the benefits of it are studied. This proposed algorithm causes reduction of hardware and improvement in time resolution in the two-step data converter. In the first stage of proposed structure, a TDC delay line is used. The second stage in proposed structure consists of some logical gates and a counter. To check the proposed algorithm, it is simulated by Hspice and Matlab. In comparison with another algorithm, in valid references, reduction in hardware and improvement in time resolution are comfirmed in proposed algorithm.

Time-to-Digital Converter (TDC) is one of the main blocks of a Digital phased Locked Loops. This element is used for accurate measuring of time intervals and converting them to digital code. This thesis aimed to improve resolution, dynamic range, delay stages per step, figure of merit and equal number of bits in comparison to previous structures. This thesis proposed a new structure calling three-dimensional Vernier Time-to-Digital converter. This structure using three delay lines and three Vernier planes, significantly increases the number of quantization levels based on the concept of Vernier plane. The proposed structure can be arranged in two different ways depending on the purpose of the design, either achieve to best possible resolution or best possible dynamic range. To implement the proposed idea, two samples of three-dimensional and one sample of two-dimensional Vernier TDC simulated with 90nm CMOS by Cadence and different parameters of them are compared. In the first scheme (designed for access to best possible resolution) TDC covers 854.4ps input range by 4.8ps resolution. In the second scheme (designed for access to best possible dynamic range) TDC covers 1134ps input range by 6ps resolution. Proposed TDC can improve resolution, dynamic range, equal number of bits and figure of merit in comparison with previous structures, especially two-dimensional TDC.

With the advancement of CMOS technology power supply voltage is reduced and switching speed is increased. Reducing the supply voltage, makes it difficult to achieve high-precision for valtage-domain data converters. On the contrary, increasing switching speed results better performance in time-domain data converters. In VCO-based data converters, signals can be quantized in time domain. In addition, these converters have inherent noise shaping property. The benefit raised made this converters interesting for researchers. Several structures for improving performance of these converters have been presented. MASH structure increasesboth the efficiency and no need for analog components in implementation. In this thesis two kinds of MASH structure have been analyzed and optimized. The first structure contains VCO and VC-GRO that introduces a method to improve resolution and also a differential structure nonlinear effects, in which its signal to noise ratio has been increased by 26dB (equivalent to 4.32 bit in ENOB) and its signal to noise and distortion has been increased 20.5dB. The second structure is a two stage MASH with GRO that proposes a method to improvement resolution, in which its signal to noise ratio has been increased by 26.6dB (equivalent to 4.41 bit in ENOB). Forthermore, Common method to improve resolution of MASH structure consume high power. But in the proposed method, resolution has been improved with no apparent increase in power consumption.

 Sigma Delta analog to digital data converter is a common ADC with high resolution performance. By using noise shaping function, Sigma Delta ADC pushes in-band frequency noise to higher frequencies where it is outside the band of interest and as a result it improves output signal to noise ratio (SNR) and ENOB. These converters consist of an oversampling modulator followed by digital decimation filters. The main functions of these filters are removing out of band quantization noise and reducing modulator's output bit-stream. There are few literuture in the field of Quadrature Sigma Delta ADC. Besides, in most of these works, the IF signal downsampled to the base band and as a consequence digital decimation design is the same as the decimation filter in low pass Sigma Delta ADC. However, In this work, a design procedure of digital decimation filter for quadrature Sigma Delta ADC is presented and then the filter transfer function gets optimized with the aim of reducing quantization noise in folding bands. In optimization process, zeros locations of filter transfer function assume as variables of cost function in genetic algorithm process. Finally, the density of quantization noise in folding bands calculated for both using optimized filer and standard filter used in other works in the same field as this work. The results show that improvement in reducing quantization noise is very satisfying.